Network and storage array test devices, such as protocol emulators and/or protocol analyzers are often required to receive data and store the data in internal memory at line rates. For example, a protocol emulator that emulates a storage array connected via a storage area network may be required to receive and store data at fiber channel line rates on the order of gigabits per second or tens of gigabits per second.
In light of the high line rates encountered by network and storage array test devices, it is desirable to utilize an efficient mechanism for receiving data into host (test device) memory. One possible way to receive data into host memory is to use the host central processing unit (CPU) to control the receiving of data into memory. Using the host CPU to control the receiving of data into memory is undesirable because the host CPU is not optimized for such high speed transfers and is often busy performing other tasks.
Another possible mechanism for receiving high speed data into host memory is to use direct memory access or DMA. When using DMA, special purpose hardware, referred to as a DMA controller, controls the writing of data into host memory, with minimal involvement by the host CPU. As a result, the host CPU is free to perform other tasks, and the DMA controller can be optimized for high speed data transfer required, for example, when the host device is emulating a storage area network.
In order to perform a DMA transfer, the DMA controller must be provided with the address in memory where data is to be written and the amount of space available beginning at the memory address. Scatter lists are one mechanism used in providing address and buffer information to a DMA controller. A scatter list is a linked list of pointers to host memory and corresponding buffer sizes. A scatter list may be created by host system software for storing data received from an I/O device, such as a protocol offload engine (specialized hardware that is design to extract protocol data from packets received over a network). Thousands of scatter list entries may be created by a protocol emulator or analyzer to monitor sessions of interest. These entries may be stored in host system memory. Because it is desirable to offload data transfer from the host CPU, there exists a need for an efficient way to provide scatter list information to the DMA controller.
One possible way to provide scatter list information to the DMA controller is to cache scatter list entries in memory of the protocol offload engine or other device that interfaces with the DMA controller. However, because memory may be limited on the protocol offload engine, only portions of the scatter list can be cached. As a result, the cache on the protocol offload engine must be frequently refilled. In addition, once a scatter list entry is used or partially used by writing data that fully or partially fills a location in host memory corresponding to a scatter list entry, a possible implementation is to write the partially used scatter list entry back to host system memory and subsequently receive a new scatter list from host system software that reflects the partially used entry. Requiring writes to host system memory each time a scatter list is partially used and requiring a subsequent read from host system memory to use the remainder of a partially used entry is undesirable, as the reads and writes to host system memory slow protocol offload engine performance.
Accordingly, in light of these difficulties, there exists a need for methods, systems, and computer readable media for caching and using scatter list metadata to control DMA receiving of network protocol data.